分享：最新Hotfix_SPB17.20.021_wint_1of1补丁

Fixed CCRs: SPB 17.2 HF021
06-3-2017
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CCRID   Product            ProductLevel2 Title
========================================================================================================================================================
1401318 ADW                DBEDITOR      Bulk Edit - Previously modified cells do not turn blue when selected
1621446 ADW                DBEDITOR      Bulk Edit - sorting highlights incorrect cells to mark them as changed
1743997 ADW                LIB_FLOW      Match file for standard models is incorrect
1746052 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when applying no drc property
1736067 ALLEGRO_EDITOR     DRC_CONSTR    Interlayer checks not reporting DRCs between cline and mask layer
1738587 ALLEGRO_EDITOR     EDIT_ETCH     Line width changing on slide for ETCH - Conductor (Not on a NET)
1745277 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on using the slide command
1747942 ALLEGRO_EDITOR     EXTRACT       Fabmaster Out does not export arc in pad_shape
1737202 ALLEGRO_EDITOR     GRAPHICS      Setting the variable display_raster_ops
1744042 ALLEGRO_EDITOR     GRAPHICS      Unused pad suppression is not working on few nets
1703848 ALLEGRO_EDITOR     INTERFACES    IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty
1743899 ALLEGRO_EDITOR     MANUFACT      Glossing dangling vias crashes PCB Editor
1744467 ALLEGRO_EDITOR     OTHER         The 'logical_op_new' variable is not displayed in User Preferences Editor
1748520 ALLEGRO_EDITOR     OTHER         TDP fails to load on an empty database
1748581 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor crashes when changing default pad geometry
1751469 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor crashes/freezes when browsing for a shape symbol
1725948 ALLEGRO_EDITOR     SHAPE         Shape differences after conversion from release 16.6 to release 17.2-2016
1729306 ALLEGRO_EDITOR     SHAPE         Seting shape_rki_autoclip variable causes no void to be generated
1698876 ALLEGRO_EDITOR     UI_GENERAL    Tabs are large and text is compressed in release 17.2-2016
1698883 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors
1707933 ALLEGRO_EDITOR     UI_GENERAL    axlUIMenuFind not locating menu as per x_location
1741460 ALLEGRO_EDITOR     UI_GENERAL    Right-click, context menu options grayed in some cases after choosing Edit - Copy
1747588 ALLEGRO_EDITOR     UI_GENERAL    Interacting with PCB Editor by sending messages is not working
1747488 APD                EDIT_ETCH     Route connect is improperly affecting existing routes in locked high speed via structures
1750182 APD                STREAM_IF     The stream out settings are not saved
1752067 ASI_SI             GUI           Links to differential waveforms do not work in Sigrity SI report
1752131 CONCEPT_HDL        COMP_BROWSER  Symbol view in part manager doesn't match the symbol version
1754116 CONCEPT_HDL        COMP_BROWSER  Default Symbol selected is n°2 instead of n°1 in component Browser
1754949 CONCEPT_HDL        COMP_BROWSER  Part Information Manager displays preview window with the wrong symbol and missing footprint
1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
1750916 CONCEPT_HDL        CORE          DE-HDL crashes when trying to uprev a project in release 17.2-2016
1711487 CONCEPT_HDL        INFRA         Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design
1746915 CONSTRAINT_MGR     CONCEPT_HDL   Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
1743523 CONSTRAINT_MGR     DATABASE      Suppress warning pop-ups from the constraint automation script
1746941 CONSTRAINT_MGR     UI_FORMS      'Go to Source' from DRC tab is not working in release 17.2-2016
1753010 ECW                METRICS       Metrics not getting collected due to old license in use
1713052 FSP                GUI           Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
1719099 FSP                GUI           Net naming wrong after building block
1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner
1720479 PSPICE             ENVIRONMENT   Probe window does not open consistently on Windows 10 systems
1723411 PSPICE             ENVIRONMENT   Probe window does not open consistently on Windows 10 systems
1746628 PSPICE             ENVIRONMENT   PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
1745976 SIG_INTEGRITY      GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing
1690820 SIP_LAYOUT         PLATING_BAR   Cannot add fillets to pads with plating bars in release 17.2-2016
1725042 SIP_LAYOUT         PLATING_BAR   Creating a plating bar removes dynamic fillets
1747534 SIP_LAYOUT         SHAPE         Moving fiducial crashes SiP Layout

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起个大早，感谢小编的无私奉献

感謝大大的分享了..

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谢谢小编分享！

学习学习。

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谢谢小编分享！

跟不上了

谢谢！  谢谢！  谢谢！重要的说三遍

能转16.6嘛:):)

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