我的也生不成网表，急！大家一起来找错哦！

我用的是concept hdl，画的是PCI卡，用两DSP，他们都在原理图的第4页，画完执行export physic...。出现对话框内容如右："error:pxl failed,unabie to pakeage the design.do you wish to view the pxl.log file". 接着点击"是”弹出写字板一片空白，也就是无法看.pxl文档，  点击"view result"的“pxl.mrk内容如下：

(marker_file
 (version 5.0)
 (markers
  (
   (tool "Packager-XL")
   (class "LOGICAL")
   (severity 40)
   (error_num 1051)
   (short_msg "E: Cannot find physical part TMS320VC5501.
")
   (long_msg "Error (PXL): Cannot find physical part TMS320VC5501.
       Schematic instance: @PCIPROJECT_LIB.PCIDESIGN(SCH_1)AGE1_I1@PCIPROJECT_LIB.TMS320VC5501(CHIPS)
")
   (location
    (
     (object_kind "instance")
     (canonical_name "_！drawerror inst I1;")
     (parent_canonical_name "DRAWERROR inst I1")
     (drawing_name "@pciproject_lib.pcidesign(sch_1):page1")
    )
   )
  )
  (
   (tool "Packager-XL")
   (class "LOGICAL")
   (severity 40)
   (error_num 1052)
   (short_msg "E: No ppt part selection because inst has no physical part.
")
   (long_msg "Error (PXL): No ppt part selection because inst has no physical part.
       Schematic instance: @PCIPROJECT_LIB.PCIDESIGN(SCH_1)AGE1_I1@PCIPROJECT_LIB.TMS320VC5501(CHIPS)
")
   (location
    (
     (object_kind "instance")
     (canonical_name "_！drawerror inst I1;")
     (parent_canonical_name "DRAWERROR inst I1")
     (drawing_name "@pciproject_lib.pcidesign(sch_1):page1")
    )
   )
  )
 )

点击“view result"中的“pxl.dbg",内容如下：

Log File: C:\DOCUME~1\WANGXU~1\LOCALS~1\Temp\s734.
Markers File: C:\DOCUME~1\WANGXU~1\LOCALS~1\Temp\s734.1
Debug File: C:\DOCUME~1\WANGXU~1\LOCALS~1\Temp\s734.3
     Debug[0] := TRUE
Elapsed time since start = (00:00:00)

 **************************************************************
 *  End processing project file and command line  (00:00:00)  *
 **************************************************************

EDB info: Null connection to port clkout in instance page1_i1.
EDB info: Null connection to port eclkin in instance page1_i1.
EDB info: Null connection to port emifclks in instance page1_i1.
EDB info: Null connection to port emu in instance page1_i1.
EDB info: Null connection to port \emu1/of  in instance page1_i1.
EDB info: Null connection to port \hcs*  in instance page1_i1.
EDB info: Null connection to port \hint*  in instance page1_i1.
EDB info: Null connection to port hpiena in instance page1_i1.
EDB info: Null connection to port \hr/w#  in instance page1_i1.
EDB info: Null connection to port hrdy in instance page1_i1.
EDB info: Null connection to port \iack*  in instance page1_i1.
EDB info: Null connection to port \nmi#/wdtout  in instance page1_i1.
EDB info: Null connection to port pvdd in instance page1_i1.
EDB info: Null connection to port \reset*  in instance page1_i1.
EDB info: Null connection to port rx in instance page1_i1.
EDB info: Null connection to port scl in instance page1_i1.
EDB info: Null connection to port sda in instance page1_i1.
EDB info: Null connection to port tck in instance page1_i1.
EDB info: Null connection to port tdi in instance page1_i1.
EDB info: Null connection to port tdo in instance page1_i1.
EDB info: Null connection to port test in instance page1_i1.
EDB info: Null connection to port tms in instance page1_i1.
EDB info: Null connection to port \trst*  in instance page1_i1.
EDB info: Null connection to port tx in instance page1_i1.
EDB info: Null connection to port x in instance page1_i1.
EDB info: Null connection to port \x2/clkin  in instance page1_i1.
EDB info: Null connection to port xf in instance page1_i1.

 *************************
 *  Loading State Files  *
 *************************

Elapsed time since start = (00:00:00)

 *****************************************
 *  End loading State Files  (00:00:00)  *
 *****************************************

 ****************************************
 *  Starting to assign physical parts.  *
 ****************************************

 **************************************************
 *  FATAL ERROR PackagerXL exiting with status 2  *
 **************************************************

我已作了5501的pin mapping ,现在无法打包，不知何故，恳请各位指正，谢谢！

pxl.dbg指出DSP有未接管脚，然那些脚我在原理图中已接，两个档都将错误的矛头直指dsp，我做的第一步是将我在原理图中建TMS320VC5501这个库调入另一幅简单原理图，但能打包成功，甚为奇怪！