- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
求助,网络表刀入后在PCB上看不到元件
录入：edatop.com 点击：
一个很简单的电话,不过20个元件,元件封装是利用这个坛子上的一个大侠做的自动生成器里的,生成网络表后,在allegro下刀入,没什么错误提示,就是看不到元件的封装和预线啊.
Cadence Design Systems, Inc. netrev 15.5 Thu Aug 31 21:26:06 2006
(C) Copyright 2002 Cadence Design Systems, Inc.
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
MISSING SYMBOL AS ERROR FALSE;
SCHEMATIC_DIRECTORY 'F:/ALLEGRO';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'C:/Documents and Settings/mama/桌面/8051.brd';
NEW_BOARD_NAME 'C:/Documents and Settings/mama/桌面/8051.brd';
CmdLine: netrev -$ -5 -i F:/ALLEGRO -y 1 C:/Documents and Settings/mama/桌面/#Taaaaaa00216.tmp
------ Preparing to read pst files ------
Starting to read F:/ALLEGRO/pstchip.dat
Finished reading F:/ALLEGRO/pstchip.dat (00:00:00.00)
Starting to read F:/ALLEGRO/pstxprt.dat
Finished reading F:/ALLEGRO/pstxprt.dat (00:00:00.00)
Starting to read F:/ALLEGRO/pstxnet.dat
Finished reading F:/ALLEGRO/pstxnet.dat (00:00:00.01)
------ Oversights/Warnings/Errors ------
------ Library Paths ------
MODULEPATH = C:\MYSYM\
PSMPATH = C:\MYSYM\
PADPATH = C:\MYSYM\
------ Summary Statistics ------
netrev run on Aug 31 21:26:06 2006
DESIGN NAME : '8051'
PACKAGING ON Jun 17 2005 00:56:10
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
No error detected
No oversight detected
No warning detected
cpu time 0:00:17
elapsed time 0:00:00
谁能大概指点一下,错出在什么地方,我是新手,不是很会用这个软件.
你用place－manually去选你的元件才能放出来，不行在看看log提示
