- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
出网表的问题
下面这个是DRC
********************************************************************************
*
* Design Rules Check
*
********************************************************************************
Checking Pins and Pin Connections
--------------------------------------------------
Checking Schematic: SCHEMATIC1
--------------------------------------------------
Checking Electrical Rules
WARNING [DRC0004] Possible pin type conflict U27,SCLK0 Output Connected to Bidirectional: SCHEMATIC1, 3: CPU2_OK (48.26, 109.22)
Checking for Unconnected Nets
Checking for Invalid References
Checking for Duplicate References
Check Bus width mismatch
导网表就出现下面的东东,没有生成一个网络
********************************************************************************
*
* Create Netlist
*
********************************************************************************
Netlist Format: allegro.dll
Design Name: C:\DOCUMENTS AND SETTINGS\ADMINISTRATOR\桌面\GPSR1001029.DSN
[FMT0023] Lib/part pin mismatch U11 pin 6
[FMT0018] Errors processing intermediate file
请高手们指点一下
问题解决了,重新编辑一下U11就好了.谢谢各位的关注.
Cadence Allegro 培训套装,视频教学,直观易学
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