• 易迪拓培训,专注于微波、射频、天线设计工程师的培养
首页 > 电子设计 > PCB设计 > Allegro PCB技术问答 > 求助生成网络表时出错的问题

求助生成网络表时出错的问题

录入:edatop.com     点击:

谁能帮我看下 我在CADENCE 里画的原理图  却怎么也生成不了网络表.提示如下:

Spawning... "D:\CADENCE\PSD_15.0\tools\capture\pstswp.exe" -pst -d "F:\张峰\6203终极设计\6203系统终极原理图绘制.dsn" -n "F:\张峰\6203终极设计\allegro" -c "D:\CADENCE\PSD_15.0\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
#1 Warning [ALG0016] Part Name "PCI CONNECTOR_PCI5V32_PCI CONNECTOR" is renamed to "PCI CONNECTOR_PCI5V32_PCI CONNE".
#2 Warning [ALG0016] Part Name "SN74CBTD16211_DL56_SN74CBTD16211" is renamed to "SN74CBTD16211_DL56_SN74CBTD1621".
#3 Warning [ALG0016] Part Name "EPM128SLC1001_QFP100_EPM7128SLC100-TQFP" is renamed to "EPM128SLC1001_QFP100_EPM7128SLC".
#4 Warning [ALG0016] Part Name "SN74ALB16244_TSSOP48-DGG_SN74ALB16244" is renamed to "SN74ALB16244_TSSOP48-DGG_SN74AL".
#5 Warning [ALG0016] Part Name "SN74LVTH162245_TSSOP48-DGG_SN74LVTH162245" is renamed to "SN74LVTH162245_TSSOP48-DGG_SN74".
Scanning netlist files ...
Loading... F:\张峰\6203终极设计\allegro/pstchip.dat
Loading... F:\张峰\6203终极设计\allegro/pstchip.dat
Loading... F:\张峰\6203终极设计\allegro/pstxprt.dat
#38 DDB_ERROR: Terminating character ':' not found on line 11.
              DDB_INFO: File F:\张峰\6203终极设计\allegro/pstxprt.dat not loaded.
Error: Line 11 in file F:\张峰\6203终极设计\allegro/pstxprt.dat:
   Error loading the
 parts list file 
 Detected in function: ddbLoadPstXFiles
#6 Error   [ALG0036] Unable to read logical netlist data.

Exiting... "D:\CADENCE\PSD_15.0\tools\capture\pstswp.exe" -pst -d "F:\张峰\6203终极设计\6203系统终极原理图绘制.dsn" -n "F:\张峰\6203终极设计\allegro" -c "D

谁能告诉我这是因为什么啊?

急救

Cadence Allegro 培训套装,视频教学,直观易学

上一篇:allegro15.5-part developer问题
下一篇:SPECCTRA's log是什么文件

PCB设计培训课程推荐详情>>

  网站地图