capture+allegro

大哥！你的比喻很好啊！主要是因为他们是一家的啊！

小编说的CAPTURE是指ALLEGRO里面自带的CAPTURE CIS还是ORCAD CAPTURE呢?

现在初学，搞不清楚他们的关系，想请教下怎么从CAPTURE CIS进行网表的转换，加载到ALLEGRO里面，请小编指教。多谢！

哈哈！小编说得有意思！

小编老大，你比我还狠，我只是说 一个漂亮的女人却和别人的丈夫好上了，你却说他们是一家，那就存在社会伦理问题了！

哎，越说越黑！

capture就是capture，不能因为她和allegro扯上关系，就说她不是layput plus的原配了 ,只是在与allegro发生关系时,要选择适当的suite.

做网表时请注意以下细节，毕竟allegro不是一个随便的人：

Best practices for preparing a library for Capture-Allegro PCB Editor
flow
􀂃 Limit part and pin names to 31 characters
􀂃 Use upper case characters for part/symbol names, part references
designators, and pin names
􀂃 Do not use special characters to assign part names, references
designators, and pin names
􀂃 Do not use duplicate pin names for pins other than power pins
􀂃 For multiple power pins with the same pin names, do not make some
pins visible and other invisible
􀂃 Do not use "0" as a pin number
Best practices for Capture design for Allegro PCB Editor
􀂃 While defining a net list alias or a net name
• Keep the maximum length of a net name or alias up to 31
characters
• Do not use lower case or special characters in a net name
􀂃 Avoid using "Power Pins Visible" property at design level
􀂃 Use net to connect pins
• Leave room for assigning a net name. Pin-to-pin connection
changes the net name when a user moves a component
􀂃 Run the Capture DRC command before generating Allegro PCB Editor
netlist
􀂃 Set path for Allegro PCB Editor footprint before running Netrev
Best practices for smooth back annotation
􀂃 Do not change design name, hierarchical block names, or reference
designators in Capture after board files creation
􀂃 Do not edit a part from schematic in Capture after board file
creation
􀂃 Do not replace cache as it changes the Source library name and part
name, in capture
􀂃 Do not change the values of component definition properties in
capture after board files creation
􀂃 Do not change Design file/root schematic/hierarchical block names
in Capture after board file creation
􀂃 Do not add or delete components to or from the schematic design
immediately after the board file creation. Add or delete components
after finishing the back annotation process
- 2 -
􀂃 Do not add any additional components in Allegro PCB Editor. Instead,
add components in Capture and take them to Allegro PCB Editor
􀂃 Do not add, rename, or delete a net in Allegro PCB Editor
􀂃 Do not change the format for reference designators for parts in
Allegro PCB Editor as <Alphabet(s)><Numeric><Alphabet(s)> or
><Alphabet(s)>-<Alphabet(s)>
􀂃 Run Allegro PCB Editor Dbdoctor before running Back annotation by
selecting the Database Check command from the Tools menu in Allegro
PCB Editor
􀂃 Make backups of the original design before updating the design with
the swap information in Capture
􀂃 Back annotate the design immediately after making the board file.
Though it does not a mandatory step, back annotating the design
before placing components helps avoid problems in back-annotation
at a later stage.
If back annotation at this stage generates an empty swap file, you
can proceed with placing and routing the board file. In case any
problems are detected, you must correct them in the design file and
generate the board file again until an empty swap file is generated.

你生成网表的时候就会有选择了

allegro 里的capture cis其实就是orcad，只是orcad被cadence收购后改了个名字而已……

呵呵呵小编的比喻很有意思啊...这里不需要认真，真好呵呵

小编说的对呀,希望以后在论坛中看到它们的"原配"出现的多一点.