用concept HDL怎样做原理图库？

大家好！

　　　请问用concept HDL怎样做原理图库?做库时要注意些什么问题啊！

我是初学者，如果用别人做好的原理图库调出来用就不会出问题，但自已做的原理图库调出来用在打包导入Ａllegro时就会出错！请高手指点！

麻烦

几句话讲不明白，找文档看吧！做熟后会发现它很方便

我现在Capture的库也先用它做，再格式转换.

ddwu:

      你好！

      请问你有没有这方面的电子文档啊！我找好久了都找不到啊！能否转我一份呢！

我的email:caisp2000@163.com;

万分感激！

    Cadence Design Systems, Inc.
    Packager-XL 15.20-p001 WIN32 28-May-2004 12:00:00 IST
    (C) Copyright 1994, Cadence Design Systems, Inc.

    Run on Fri Jul 27 21:32:34 2007

 **********************************************
 *  Processing project file and command line  *
 **********************************************

    ANNOTATE  'BODY' 'PIN'
    COMP_DEF_PROP  'ALT_SYMBOLS' 'JEDEC_TYPE' 'NC_PINS' 'MERGE_NC_PINS'
                   'POWER_GROUP' 'POWER_PINS' 'MERGE_POWER_PINS' 'PINCOUNT'
    COMP_INST_PROP  'GROUP' 'ROOM' 'REUSE_INSTANCE' 'REUSE_ID' 'REUSE_NAME'
                    'SIGNAL_MODEL' 'DEFAULT_SIGNAL_MODEL'
                    'VOLT_TEMP_SIGNAL_MODEL'
    SUPPRESS_GLOBAL_SHORT_CHECK OFF
    DEBUG    0
    DEFAULT_PHYS_DES_PREFIX U
    FEEDBACK  'OFF'
    MAX_ERRORS 999
    NET_NAME_CHARS   @  -  ！  #  %  &  (  )  *  .  /  :  ?  [  ]  ^  _  `  +
                     =  >  0  1  2  3  4  5  6  7  8  9
    NET_NAME_LENGTH 31
    NUM_OLD_VERSIONS 3
    OPTIMIZE OFF
    REUSE_REFDES ON
    OPF_OPTIMIZATION OFF
    HARD_LOC_SEC OFF
    FORCE_PTF_ENTRY OFF
    REGENERATE_PHYSICAL_NET_NAME OFF
    SCH_POWER_GROUP_WINS_OVER_PPT OFF
    NULL_OPT_VALID OFF
    USE_VECTOR_NOTATION ON
    FILTER_ECS_FROM_XNET ON
    OUTPUT  'ON'
    PACKAGE_PROP  'GROUP' 'ROOM'
    PART_TYPE_LENGTH 31
    REF_DES_LENGTH 31
    REPACKAGE OFF
    ELECTRICAL_CONSTRAINTS OFF
    OVERWRITE_CONSTRAINTS OFF
    RUN_DIR ./worklib/7294/packaged/
    STRICT_PACKAGE_PROP  'REUSE_INSTANCE'
    USE_LIBRARY_PPT ON
    USE_STATE ON
    WARNINGS ON
    LIBRARY  '7294_lib' 'element' 'standard' 'caisp'
    VIEW_PTF part_table
    VIEW_PACKAGER packaged
    VIEW_CONSTRAINTS constraints
    DESIGN_LIBRARY 7294_lib
    DESIGN_NAME 7294
    VIEW_CONFIG_PHYSICAL cfg_package
    SD_SUFFIX_SEPARATOR _

 **************************************************************
 *  End processing project file and command line  (00:00:00)  *
 **************************************************************

Creating Configuration "cfg_package" for Design "7294"

Loading C:\Cadence\SPB_15.2\share\cdssetup\cdsprop.tmf.
Loading C:\Cadence\SPB_15.2\share\cdssetup\cdsprop.paf.

 *********************************
 *  Loading the design database  *
 *********************************

 #1  ERROR(346): Unable to expand this design for packaging.  The chips view w~
as not found for cell 'cap' in library 'caisp'.

1 errors detected
No warnings detected
    Start time   21:32:34
    End time     21:32:34
    Elapsed time  0:00:00

 **************************************************
 *  FATAL ERROR PackagerXL exiting with status 2  *
 **************************************************