- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
求教:导入网络表错误....
我已经将自己做的封装复制到d:\Cadence\SPB_15.2\share\pcb\pcb_lib\symbols中。为什么导入ALLEGRO还有如下错误:RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
MISSING SYMBOL AS ERROR FALSE;
SCHEMATIC_DIRECTORY 'D:\OrCAD\OrCAD_10.5';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'D:\ CadenceTEMP\t.brd';
NEW_BOARD_NAME 'D:\ CadenceTEMP\t.brd';
CmdLine: netrev -$ -5 -i D:\OrCAD\OrCAD_10.5 -y 1 D:\ CadenceTEMP\#Taaaaaa01172.tmp
------ Preparing to read pst files ------
#1 ERROR(24) File not found
Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Nov 5 10:02:02 2007
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
2 errors detected
No oversight detected
No warning detected
cpu time 0:00:06
elapsed time 0:00:00