ERROR: PXL failed. Unable to package the design,请各位高手帮忙。急

小弟刚开始学CADENCE，用的是CADENCE 15.2,在利用Allegro Design Entry HDL 打包电路的时候不能完成，请各位高手指教，谢谢。一下是PXL中的文件：

    Cadence Design Systems, Inc.
    Packager-XL 15.20-p001 WIN32 28-May-2004 12:00:00 IST
    (C) Copyright 1994, Cadence Design Systems, Inc.

    Run on Tue Jul 24 18:21:35 2007

 **********************************************
 *  Processing project file and command line  *
 **********************************************

    ANNOTATE  'BODY' 'PIN'
    COMP_DEF_PROP  'ALT_SYMBOLS' 'JEDEC_TYPE' 'NC_PINS' 'MERGE_NC_PINS'
                   'POWER_GROUP' 'POWER_PINS' 'MERGE_POWER_PINS' 'PINCOUNT'
    COMP_INST_PROP  'GROUP' 'ROOM' 'REUSE_INSTANCE' 'REUSE_ID' 'REUSE_NAME'
                    'SIGNAL_MODEL' 'DEFAULT_SIGNAL_MODEL'
                    'VOLT_TEMP_SIGNAL_MODEL'
    SUPPRESS_GLOBAL_SHORT_CHECK OFF
    DEBUG    0
    DEFAULT_PHYS_DES_PREFIX U
    FEEDBACK  'OFF'
    MAX_ERRORS 999
    NET_NAME_CHARS   @  -  ！  #  %  &  (  )  *  .  /  :  ?  [  ]  ^  _  `  +
                     =  >  0  1  2  3  4  5  6  7  8  9
    NET_NAME_LENGTH 31
    NUM_OLD_VERSIONS 3
    OPTIMIZE OFF
    REUSE_REFDES ON
    OPF_OPTIMIZATION OFF
    HARD_LOC_SEC OFF
    FORCE_PTF_ENTRY OFF
    REGENERATE_PHYSICAL_NET_NAME OFF
    SCH_POWER_GROUP_WINS_OVER_PPT OFF
    NULL_OPT_VALID OFF
    USE_VECTOR_NOTATION ON
    FILTER_ECS_FROM_XNET ON
    OUTPUT  'ON'
    PACKAGE_PROP  'GROUP' 'ROOM'
    PART_TYPE_LENGTH 31
    REF_DES_LENGTH 31
    REPACKAGE OFF
    ELECTRICAL_CONSTRAINTS OFF
    OVERWRITE_CONSTRAINTS OFF
    RUN_DIR e:/Cadence/SPB_15.2/share/library/standard/mydesign/packaged/
    STRICT_PACKAGE_PROP  'REUSE_INSTANCE'
    USE_LIBRARY_PPT ON
    USE_STATE ON
    WARNINGS ON
    LIBRARY  'myproject_lib' 'standard' '1_shot' '100e' '100el' '100elt' '100k'
             '100kh' '100lvel' '10e' '10el' '10elt' '10k' '10kh' '54alsttl'
             '54asttl' '54fact' '54fast' '54fct' '54hcmos' '54lsttl' '54sttl'
             '54tiac' '54ttl' '7400' '74ac' '74act' '74als' '74as' '74f' '74h'
             '74hc' '74hct' '74l' '74ls' '74s' 'a100e' 'a100el' 'a100elt'
             'a100k' 'a100kh' 'a100lvel' 'a10e' 'a10el' 'a10elt' 'a10k' 'a10kh'
             'a54alsttl' 'a54asttl' 'a54fact' 'a54fast' 'a54fct' 'a54hcmos'
             'a54lsttl' 'a54sttl' 'a54tiac' 'a54ttl' 'a74alsttl' 'a74asttl'
             'a74fact' 'a74fast' 'a74fct' 'a74hcmos' 'a74lcx' 'a74lsttl'
             'a74sttl' 'a74ttl' 'aa_igbt' 'abm' 'aclock' 'acmos' 'adv_lin'
             'agaas' 'ainterface' 'alsttl' 'amemory' 'ana_swit' 'analog'
             'analog_p' 'anl_misc' 'anlg_dev' 'apex' 'apex_pwm' 'asttl' 'asw'
             'atidttl' 'bipolar' 'bjn' 'bjnd' 'bjp' 'bjpd' 'breakout' 'buf'
             'burr_brn' 'cd4000' 'cel' 'clock' 'cmos' 'comlinr' 'contrllr'
             'cores' 'darlngtn' 'dataconv' 'di' 'dif' 'dig_ecl' 'dig_gal'
             'dig_misc' 'dig_pal' 'dig_prim' 'dih' 'diode' 'div' 'diz' 'dri'
             'ebipolar' 'ediode' 'elantec' 'element' 'epcos' 'epwrbjt' 'fact'
             'fairchild' 'fast' 'fct' 'filtsub' 'fwbell' 'gaas' 'harris' 'hcmos'
             'igbt' 'infineon' 'interface' 'ixys' 'jbipolar' 'jdiode' 'jfet'
             'jfn' 'jfp' 'jjfet' 'jopamp' 'jpwrbjt' 'jpwrmos' 'lcx' 'lin_tech'
             'linedriv' 'lsttl' 'magnetic' 'maxim' 'memory' 'mfn' 'mfp' 'misc'
             'mix_misc' 'motor_rf' 'motorsen' 'nat_semi' 'nec_mos' 'on_amp'
             'on_bjt' 'on_diode' 'on_mos' 'on_pwm' 'opa' 'opamp' 'opt' 'opto'
             'phil_bjt' 'phil_diode' 'phil_fet' 'phil_rf' 'pld' 'polyfet'
             'pspice_elem' 'pwrbjt' 'pwrmos' 'rcacmos' 'rfbjn' 'rfbjp' 'rfdio'
             'sah' 'shindngn' 'source' 'sourcstm' 'spe' 'special' 'sttl'
             'swit_rav' 'swit_reg' 'templates' 'tex_inst' 'thy1' 'thyristr'
             'tidttl' 'tline' 'ttl' 'tzb' 'vd' 'ver_HWmodels' 'vlsi' 'vr' 'xtal'
             'zetex'
    CDSPROP_FILE
    VIEW_PTF part_table
    VIEW_PACKAGER packaged
    VIEW_CONSTRAINTS constraints
    DESIGN_LIBRARY standard
    DESIGN_NAME mydesign
    VIEW_CONFIG_PHYSICAL cfg_package
    SD_SUFFIX_SEPARATOR _

 **************************************************************
 *  End processing project file and command line  (00:00:00)  *
 **************************************************************

Creating Configuration "cfg_package" for Design "mydesign"

Loading e:\Cadence\SPB_15.2\share\cdssetup\cdsprop.tmf.
Loading e:\Cadence\SPB_15.2\share\cdssetup\cdsprop.paf.

 *********************************
 *  Loading the design database  *
 *********************************

 #1  ERROR(293): Occurred in EDB on attempt to locate, load or expand the desi~
gn.  Verify you have saved your entire design.
        EDB reports:
        SIR file: standard.mydesign:sch_1 is not present
1 errors detected
No warnings detected
    Start time   18:21:34
    End time     18:21:35
    Elapsed time  0:00:01

 **************************************************
 *  FATAL ERROR PackagerXL exiting with status 2  *
 **************************************************

自己先顶下，谢谢了

不暸問題點

知道的帮忙顶一下啊