在内层走线，通过via和外层连接，验证设计时，有错误.如何处理呢

layer 3 电源层走了两对模拟差分线。通过在走线上打通孔和layer 4的电容连接。但是在verify design/connectivity中，有如下错误。看起来pads不认为通孔和走线有连接关系。请问在电源层中该如何处理这两对网络？如何把通孔和走线combine在一些？
Isolated subnets for: MIC_P
*** subnet # 1
C8.1 VIA(746.31,200.61 L1)
*** subnet # 2
C9.1 VIA(654.5,200.23 L1)
*** subnet # 3
C11.2 VIA(375.38,199.87 L1)
*** subnet # 4
C10.2 VIA(285.46,200.63 L1)
*** subnet # 5
U9.4 VIA(217.81,199.89 L1)
*** subnet # 6
U1.21 U8.1 VIA(962.41,298.17 L1)
Isolated subnets for: MIC_N
*** subnet # 1
VIA(745.93,162.08 L1) C8.2
*** subnet # 2
C13.1 VIA(560.05,162.08 L1)
*** subnet # 3
C12.1 VIA(468.62,162.08 L1)
*** subnet # 4
VIA(217.81,162.11 L1) U9.5
*** subnet # 5
C9.2 VIA(654.5,161.7 L1)
*** subnet # 6
U1.20 U8.2 VIA(989.28,271.3 L1)
Isolated subnets for: SPK_P
*** subnet # 1
C3.1 VIA(1598.36,416.91 L1)
*** subnet # 2
C2.1 VIA(1693.89,416.67 L1)
*** subnet # 3
C5.2 VIA(1961.57,416.66 L1)
*** subnet # 4
VIA(2052.77,416.66 L1) C4.2
*** subnet # 5
U5.4 VIA(2197.72,416.95 L1)
*** subnet # 6
U1.23 U4.1 VIA(1304.63,334.82 L1)
Isolated subnets for: SPK_N
*** subnet # 1
VIA(1786.78,379.07 L1) C7.1
*** subnet # 2
VIA(1877.08,378.32 L1) C6.1
*** subnet # 3
VIA(2197.48,378.69 L1) U5.5
*** subnet # 4
C3.2 VIA(1598.6,378.41 L1)
*** subnet # 5
C2.2 VIA(1693.41,378.41 L1)
*** subnet # 6
U1.24 U4.2 VIA(1331.5,307.95 L1)

如上图，PCB下部的2对差分走线和通孔。

无图无真相！

我也遇到了，怎么解决呢

Setup-Dirll Pairs