CST simulator error： the port in a PEC layer， can't be analyzed

Recently I simulated a monopole antenna with a shorted strip on a thickness of 0.2 mm of FR4 PCB board by CST simulator. And I used lump port to analyze this specific antenna. But CST simulator tell me "the port in a PEC layer, can't be analyzed".

Could anyone encounter this problem on simulating antenna by CST simulator? If so, could you tell me how to solve this problem?

Thanks in advance

Hello Cyai,

I would try the following steps :
1. Check the port location - It shouldn't be INSIDE PEC ( although in practice it can ). Instead - place it on the boundaries of the required PEC's ( Ground and Monopole i guess ).

2. Check the Meshing ! Go to the "Mesh View" - you should see the port clearly !
The meshing needs to be dense enough in the feed gap area so CST will " See " a discrete port.
BTW : It doesn't mean you have to BLOW UP the model's meshing - just try to increase the mesh ratio a little.

Good Luck,
P.

Hi,
I have had that problem too. I just extended the port (like 1mm) so that the port does not touch the substrate. You can extend it easily by adding some little rectangles and then put the port on the edge of these extensions.
I now only use waveguide ports. I never had that problem again and the results are more accurate.
If you still have problems to solve it, just send me your *.mod file and I will fix it.

elomatic@gmx.ch

ciao

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